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MITSUBISHI
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
DESCRIPTION
The M66281FP is high speed line memory that uses high performance silicon gate CMOS process technology and adopts the FIFO (First In First Out) structure consisting of 5120 words x 8 bits x 2. Since memory is available to simultaneously output 1 line delay and 2 line delay data, the M66281FP is optimal for the compensation of data of multiple lines.
FEATURES
* * * * * * * * * * Memory configuration 5120 words x 8 bits x 2 (dynamic memory) High speed cycle 25 ns (Min.) High speed access 18 ns (Max.) Output hold 3 ns (Min.) Reading and writing operations can be completely carried out independently and asynchronously. Variable length delay bit Input/output TTL direct connection allowable Output 3 states Q00 - Q07 1 line delay Q10 - Q17 2 line delay
APPLICATION
* Digital copying machine, laser beam printer, high speed facsimile, etc.
When write reset input WRESB is set to "L", the write address counter of memory only for 1 line delay data is initialized. When read enable input REB is set to "L", the contents of memory only for 1 line delay data are output to data outputs Q00 to Q07 and the contents of memory only for 2 line delay data are output to Q10 to Q17 in synchronization with a rising edge of read clock input RCK to perform reading operation. When this is the case, the read address counters of memory only for 1 line delay data and memory only for 2 line delay data are incremented simultaneously. In addition, data of Q00 to Q07 is written into memory only for 2 line delay data in synchronization with a rising edge of RCK. When this is the case, the write address counter of memory only for 2 line delay data is then incremented. When REB is set to "H", operation for reading data from memory only for 1 line delay and from memory only for 2 line delay data is inhibited and the read address counter of each memory stops. Outputs Q00 to Q07 and Q10 to Q17 are placed in a high impedance state. In addition, the write address counter of memory only for 2 line delay data then stops. When read reset input RRESB is set to "L", the read address counters of memory only for 1 line delay data as well as the write address counter and read address counter of memory only for 2 line delay data are then initialized.
FUNCTION
When write enable input WEB is set to "L", the contents of data inputs D0 to D7 are written into memory only for 1 line delay data in synchronization with a rising edge of write clock input WCK to perform writing operation. When this is the case, the write address counter of memory only for 1 line delay data is incremented simultaneously. When WEB is set to "H", the writing operation is inhibited and the write address counter of memory only for 1 line delay data stops.
PIN CONFIGURATION (TOP VIEW)
35 WRESB 34 WCK 36 WEB 33 GND 38 NC 37 NC 32 VCC 26 NC 25 NC 24 NC 23 D5 22 D6 21 D7 20 GND 19 VCC 18 Q17 17 Q16 16 Q15 15 NC 31 D0 30 D1 29 D2 28 D3 27 D4
NC 39 RCK 40 RRESB 41 REB 42 GND 43
M66281FP
VCC 44 Q00 45 Q01 46 Q02 47 NC 48 Q12 11 Q11 10 Q13 12 Q14 13 Q03 2 Q04 3 Q05 4 Q06 5 Q07 6 GND 7 VCC 8 Q10 9 NC 14 NC 1
Outline 48P6S-A(QFP)
NC : No connection
1
2 Data inputs D0 to D7 Data outputs Q0 to Q7 Data outputs Q10 to Q17 29 28 27 23 22 21 45 46 47 2 3 4 5 6 9 10 11 12 13 16 17 18 Input buffer Output buffer 42 REB Read enable input 41 RRESB Read reset input Read control circuit Read address counter Write address counter Memory Array 5120 words x 8 bits x 2 Memory only for 1 line delay data Memory only for 2 line delay data 40 RCK Read clock input 7 GND 20 GND 33 GND 43 GND
BLOCK DIAGRAM
31
30
Write enable input
WEB 36
Write reset input WRESB 35
Write control circuit
Write clock input
WCK 34
VCC
8
VCC 19
VCC 32
MITSUBISHI
5120 x 8-BIT x 2 LINE MEMORY
VCC 44
M66281FP
MITSUBISHI
M66281FP
5120 x 8-BIT x 2 LINE MEMORY ABSOLUTE MAXIMUM RATINGS (Ta=0 - 70 C unless otherwise noted)
Symbol Vcc VI VO Pd Tstg Parameter Supply voltage Input voltage Output voltage Power dispersion Storage temperature Conditions Ratings -0.3 - +4.6 -0.3 - VCC+0.3 -0.3 - VCC+0.3 540 -55 - 150 Unit V V V mW C
Value based on the GND pin Note
Note : Ta=0 - 63C. Ta > 63C are derated at -9mW/C
RECOMMENDED OPERATING CONDITIONS
Symbol Vcc GND Topr Parameter Supply voltage Supply voltage Operating temperature Min. 2.7 0 Limits Typ. 3.15 0 Max. 3.6 70 Unit V V C
ELECTRICAL CHARACTERISTICS (Ta=0 - 70 C, Vcc=2.7 - 3.6V, GND=0V unless otherwise noted)
Symbol VIH VIL VOH VOL IIH Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage High-level input current Conditions Min. 2.0 VCC-0.4 0.4 WEB, WRESB, WCK, REB, RRESB, RCK, D0 - D7 WEB, WRESB, WCK, REB, RRESB, RCK, D0 - D7 1.0 Limits Typ. Max. 0.8 IOH = -4mA IOL = 4mA VI = VCC Unit V V V V
A
IIL IOZH IOZL ICC CI CO
Low-level input current Off-state high-level output current Off-state low-level output current Average supply current during operation Input capacitance Off-time output capacitance
VI = GND VO = VCC VO = GND
-1.0 5.0 -5.0 150 10 15
A A A
mA pF pF
VI = VCC, GND, output open tWCK, tRCK = 25ns f = 1MHz f = 1MHz
3
MITSUBISHI
M66281FP
5120 x 8-BIT x 2 LINE MEMORY SWITCHING CHARACTERISTICS (Ta=0 - 70 C, Vcc=2.7 - 3.6V, GND=0V unless otherwise noted)
Symbol tAC tOH tOEN tODIS Access time Output hold time Output enable time Output disable time Parameter Min. 3 3 3 Limits Typ. Max. 18 18 18 Unit ns ns ns ns
TIMING REQUIREMENTS (Ta=0 - 70 C, Vcc=2.7 - 3.6V, GND=0V unless otherwise noted)
Symbol tWCK tWCKH tWCKL tRCK tRCKH tRCKL tDS tDH tRESS tRESH tNRESS tNRESH tWES tWEH tNWES tNWEH tRES tREH tNRES tNREH tr, tf tH Parameter Write clock (WCK) cycle Write clock (WCK) "H" pulse width Write clock (WCK) "L" pulse width Read clock (RCK) cycle Read clock (RCK) "H" pulse width Read clock (RCK) "L" pulse width Input data set up time for WCK Input data hold time for WCK Reset set up time for WCK/RCK Reset hold time for WCK/RCK Reset non-selection set up time for WCK/RCK Reset non-selection hold time for WCK/RCK WEB set up time for WCK WEB hold time for WCK WEB non-selection set up time for WCK WEB non-selection hold time for WCK REB set up time for RCK REB hold time for RCK REB non-selection set up time for RCK REB non-selection hold time for RCK Input pulse up/down time Data hold time (Note 1) Min. 25 11 11 25 11 11 7 3 7 3 7 3 7 3 7 3 7 3 7 3 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
20 20
Note 1: For 1 line access, the following conditions must be satisfied: WEB high-level period 20 ms - 5120 * tWCK - WRESB low-level period REB high-level period 20 ms - 5120 * tRCK - RRESB low-level period 2: Perform reset operation after turning on power supply.
4
MITSUBISHI
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
SWITCHING CHARACTERISTICS MEASUREMENT CIRCUIT
VCC
RL=1K SW1
Qn
Qn
SW2 CL = 30pF : tAC, tOH RL=1K CL = 5pF : tOEN, tODIS
Input pulse level Input pulse up/down time Judging voltage Input Output
: 0 - 3V : 3 ns : 1.3V : 1.3V(However, tODIS(LZ) is judged with 10% of the output amplitude, while tODIS(HZ) is judged with 90% of the output amplitude.) Load capacitance CL includes the floating capacity of connected lines and input capacitance of probe.
Item tODIS(LZ) tODIS(HZ) tOEN(ZL) tOEN(ZH)
SW1 Close Open Close Open
SW2 Open Close Open Close
tODIS and tOEN measurement condition
3V RCK 1.3V 1.3V GND
3V REB GND tODIS(HZ) tOEN(ZH)
Qn
90% 1.3V tOEN(ZL) tODIS(LZ) 1.3V 10%
VOH
Qn
VOL
5
MITSUBISHI
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
OPERATION TIMING
* Write cycle
n cycle
n+1 cycle
n+2 cycle
Disable cycle
n+3 cycle
n+4 cycle
WCK tWCK tWCKH tWCKL tWEH tNWES tNWEH tWES
WEB tDS tDH
Dn
(n)
(n+1)
(n+2)
(n+3)
(n+4)
WRESB = "H"
* Write reset cycle
n-1 cycle
n cycle
Reset cycle
0 cycle
1 cycle
2 cycle
WCK tWCK tNRESH tRESS tRESH tNRESS
WRESB
tDS tDH
Dn
(n-1)
(n)
(0)
(1)
(2)
WEB = "L"
6
MITSUBISHI
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
* Matters that needs attetion when WCK stops
n cycle
n+1 cycle
n cycle
Disable cycle
WCK tWCK tNWES
WEB tDS tDH
tDS tDH
Dn
(n)
(n)
Period for writing data (n) into memory
Period for writing data (n) into memory
WRESB = "H"
Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period of n+1 cycle. The writing operation is complete at the falling edge after n+1 cycle. To stop reading write data at n cycle, enter WCK before the rising edge after n+1 cycle. When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
7
MITSUBISHI
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
* Read cycle
n cycle
n+1 cycle
n+2 cycle
Disable cycle
n+3 cycle
n+4 cycle
RCK tRCK tRCKH tRCKL tREH tNRES tNREH tRES tAC REB tODIS Q0n (Q1n) (n) (n+1) (n+2) tOEN
HIGH-Z
(n+3) tOH
(n+4)
RRESB = "H"
* Read reset cycle
n-1 cycle
n cycle
Reset cycle
0 cycle
1 cycle
2 cycle
RCK tRCK tNRESH tRESS tRESH tNRESS
RRESB
tAC
Q0n (Q1n) (n-1)
(n)
(0)
(0)
(0) tOH
(1)
(2)
REB = "L"
8
MITSUBISHI
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
* Notes on reading of written data in read disable When writing operation is performed at n cycle and n+1 cycle on the writing side in the read disable period after n-1 cycle on the reading side, output at n cycle and n+1 cycle after read enable is invalid. For output at n+2 cycle and after, however, data written in the read disable period is to be output.
n-1 cycle
n cycle
n+1 cycle
n+2 cycle
n+3 cycle
n+4 cycle
n+5 cycle
n+6 cycle
n+7 cycle
WCK
tDS tDH Dn
(n-1) (n) (n+1) (n+2) (n+3) (n+4) (n+5) (n+6) (n+7)
n-1 cycle
Disable cycle
n cycle
n+1 cycle
n+2 cycle
RCK
REB
tAC
tODIS HIGH-Z
(n-1)
tOEN
Q0n (Q1n)
invalid
invalid
(n+2)
WEB = "L" WRESB = "H" RRESB = "H"
9
MITSUBISHI
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
VARIABLE LENGTH DELAY BIT
* 1 line (5120 bits) delay Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK before read cycle to easily make 1 line delay.
0 cycle WCK RCK tRESS tRESH WRESB RRESB
1 cycle
2 cycle
5118 cycle 5119 cycle
5120 cycle 5121 cycle 5122 cycle (0') (1') (2')
tDS tDH Dn
(0) (1) (2) (5117) (5118) (5119)
tDS tDH
(0') (1') (2') (3')
5120 cycle Q0n (Q1n)
tAC
tOH
(0) (1) (2) (3)
WEB, REB = "L"
* n-bit delay bit (Reset at cycles according to the delay length)
0 cycle WCK RCK tRESS tRESH WRESB RRESB
1 cycle
2 cycle
n-2 cycle
n-1 cycle
n cycle (0')
n+1 cycle (1')
n+2 cycle (2')
n+3 cycle (3')
tRESS tRESH
tDS tDH Dn
(0) (1) (2) (n-3) (n-2) (n-1)
tDS tDH
(0') (1') (2') (3')
m cycle Q0n (Q1n)
tAC
tOH
(0) (1) (2) (3)
WEB, REB = "L" m3
10
MITSUBISHI
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
* n-bit delay 2 (Slides input timings of WRESB and RRESB at cycles according to the delay length.)
0 cycle WCK RCK tRESS tRESH WRESB
1 cycle
2 cycle
n-2 cycle
n-1 cycle
n cycle
n+1 cycle
n+2 cycle
n+3 cycle
tRESS tRESH RRESB tDS tDH Dn
(0) (1) (2) (n-2) (n-1) (n)
tDS tDH
(n+1) (n+2) (n+3)
m cycle Q0n (Q1n)
tAC
tOH
(0) (1) (2) (3)
WEB, REB = "L" m3
* n-bit delay 3 (Slides address by disabling REB in the period according to the delay length.)
0 cycle WCK RCK tRESS tRESH WRESB RRESB
1 cycle
2 cycle
n-1 cycle
n cycle
n+1 cycle
n+2 cycle
n+3 cycle
tNREH tRES REB tDS tDH Dn
(0) (1) (2) (n-2) (n-1)
tDS tDH
(n) (n+1) (n+2) (n+3)
m cycle Q0n (Q1n)
HIGH-Z
tAC
tOH
invalid (1) (2) (3)
WEB = "L" m3
11
MITSUBISHI
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
* Reading shortest n-cycle write data "n" (Reading side n-2 cycle ends after the end of writing side n+1 cycle.) When the reading side n-2 cycle ends before the end of the writing side n+1 cycle, output Qn of n cycle is made invalid. In the following diagram, end of reading side n-2 cycle and end of writing side n+1 cycle overlap each other. This example can read n cycle data in the shortest time. When this is the case, reading operation at n-1 cycle is invalid.
n cycle
n+1 cycle
n+2 cycle
n+3 cycle
WCK
Dn
(n)
(n+1)
(n+2)
(n+3)
n-2 cycle
n-1 cycle
n cycle
RCK
Q0n (Q1n)
invalid (n)
* Reading longest n-cycle write data "n": 1 line delay (When writing side n-cycle <2> starts, reading side n cycle <1> then starts.) Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle <2>* overlap each other.
n cycle <1>*
0 cycle <2>*
n cycle <2>*
WCK
Dn
(n-1)<1>*
(n)<1>*
(0)<2>*
(n-1)<2>*
(n)<2>*
n cycle <0>*
0 cycle <1>*
n cycle <1>*
RCK
Q0n (Q1n)
(n-1)<0>* (n)<0>* (0)<1>* (n-1)<1>* (n)<1>*
<0>*, <1>* and <2>* indicate value of lines.
12
MITSUBISHI
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
APPLICATION EXAMPLE
Sub Scan Resolution Compensation Circuit with Laplacean Filter
M66281
N n line image data
D0
Q00
-
D7 B (n+1) line image data
Q07 X2 Adder
1 line delay
N+K {2N-(A+B)}
Subtracter
2N-(A+B)
Q10 Q17 A (n-1) line image data
-
Compensated image data XK Adder A+B (n-1) line n line (n+1) line N'=N+K { (N-A) + (N-B) } =N+K { (2N - (A+B) } K: Laplacean coefficient
2 line delay
-
Main scan direction
Sub scan direction
A
N
B
13

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